1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, it relates to a semiconductor device which is generally equal in size to a semiconductor chip in plan configuration, and in which the semiconductor chip is flip-chip connected to a wiring pattern, and a manufacturing method thereof.
2. Description of Related Art
In recent years, semiconductor applied products have rapidly advanced in size reduction, thickness reduction, and weight reduction as various mobile devices such as digital cameras and cellular phones. Accordingly, a semiconductor device has been also required to be reduced in size, and increased in density. Thus, there has been developed a semiconductor device (see, e.g., FIG. 1) referred to as a so-called chip size package (CSP) configured to be generally equal in size to a semiconductor chip thereof in plan configuration, and there have been proposed various manufacturing methods.
A conventional semiconductor device 100 which is so-called this chip size package will be explained. FIG. 1 is a sectional view of the conventional semiconductor device 100.
The semiconductor device 100 includes a semiconductor chip 101, internal connection terminal 102, a resin layer 103, a wiring pattern 104, a solder resist 106 and an external connection terminal 107.
The semiconductor chip 101 has a semiconductor substrate 109, a semiconductor integrated circuit 111, an electrode pad 112 and a protective film 113. The semiconductor substrate 109 is, for example, a laminated and divided Si wafer.
The semiconductor integrated circuit 111 is provided on one surface of the semiconductor substrate 109 shown in FIG. 2. The electrode pad 112 is provided on the semiconductor integrated circuit 111 and is electrically connected with wires provided on the semiconductor integrated circuit 111. The protective film 113 is provided on the semiconductor integrated circuit 111 and protects the semiconductor integrated circuit 111.
The resin layer 103 is provided so as to cover the protective film 113 provided on the semiconductor integrated circuit 111.
The wiring pattern 104 is formed on the resin layer 103 and has an external connection terminal provision region 104A on which the external connection terminal 107 is provided.
The internal connection terminal 102 penetrates the resin film 103 and electrically connects the electrode pad 112 provided on the semiconductor integrated circuit 111 with the wiring pattern 104 provided on the resin layer 103.
The solder resist 106 is provided so as to cover the wiring pattern 104 except for the external connection terminal provision region 104A. The external connection terminal 107 is provided on the external connection terminal provision region 104A on the wiring pattern 104.
This semiconductor device 100 is manufactured by following steps (a) through (g).
(a) Forming plurality of the semiconductor integrated circuits 111, the electrode pads 112, the protective films 113 on one semiconductor substrate 110.
(b) Forming the resin layer 103 on a substantially whole surface of the semiconductor substrate 110 except for the electrode pads 112.
(c) Forming the internal connection terminals 102 on the electrode pads 112.
(d) Forming the wiring patterns 104 on the resin layer 103 and the electrode pad 112.
(e) Forming the solder resist 106 on the substantially whole surface of the resin layer 103 so as to cover the wiring pattern 104 except for the region to be connected to the external connection terminal 107.
(f) Forming the external connection terminal 107 on the region where the wiring pattern 104 is exposed from the solder resist 106.
(g) Cutting the semiconductor substrate 110 passed through the steps (a) through (f) and dividing into the respective semiconductor chips 101. For example, as shown in FIG. 2, the semiconductor substrate 110 is divided into respective semiconductor chips 101 by cutting a scribe region B by moving the dicing blade along with a scribe line C.
When using the semiconductor device 100 obtained by the above described method, the semiconductor device 100 is heated while using and after that, is gradually cooled. In accordance with this heating/cooling cycle, the semiconductor device 100 thermally expands or thermally contracts. Generally, since the semiconductor chip 101 is made of silicon, the resin layer 103 is made of resin such as polyimide resin and thermosetting epoxy resin, and the solder resist 106 is made of resin such as epoxy resin and epoxyacrylate resin, when the semiconductor device 100 is heated or cooled, the respective layers 101, 103 and 106 expands or contracts in accordance with respective materially intrinsic coefficient of thermal expansion.
Further, since there is large difference in the coefficient of the thermal expansion between the silicon and the resin, in accordance with the heating and the cooling, the dimension of the semiconductor chip 101 made of silicon changes from the dimension of the resin layer 103 and the solder resist 106 which are made of resin.
This dimensional change generates a stress which causes a peeling of the resin layer 103 from the semiconductor chip 101. Thus, this repetitive stress caused by using of the semiconductor device 100 invites a peeling of the resin layer 103 from the semiconductor chip 101.
Generally, since the bonding force of the resin layer 103 to the semiconductor chip 101 becomes the weakest at a corner portion and the stress due to the dimensional change becomes the strongest at the same corner portion, the peeling of the resin layer 103 starts from the corner portion of the semiconductor chip 101.
Thus, there is a problem that a reliability of the semiconductor device 100 deteriorates due to the peeling of the resin layer 103 from the corner portion.
Note that when using the thermosetting resin as the solder resist, at the time of manufacturing the semiconductor device 100, accompanying with the hardening of the solder resist, contraction is caused and the dimensional change is also generated in manufacturing the semiconductor device 100. Thus, the peeling of the resist film 103 can be generated even if manufacturing the semiconductor device 100.